- Dec. 30,' 1958 D. c. HlERATH ET AL DIGITAL SYSTEMS FOR THE: UTOMATIC CONTROL oF MACHINERY Filed oo'z. 25. 1954 l9 Sheets-Sheet 2 'LNQENTORS DoRAN C. HRATH CLAUDE A. LAME CTW.
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DIGITAL sYsTEMs Fox THE AUTOMATIC coNTRoI. oF MACHINERY Filed oc'z. 25,'1954 9 Sheets-Sheet 7 DORAN ,C. HlERAIH CLAUDE A. LANE VD. C. HIERATH ETAL Dec. 30, 1958 DIGITAL sYsTEMs FOR THE: AUTOMATIC CONTROL oF MACHINERY Filed oot. 25, 1954 9 sheets-shet 9 w Q3 20mm m ...m a W 5,. E4 w A WWL. f l I i l I l l I I l i l I ...J-LA llllll E m W R A o L DC a 1 I I ooo. 82x w mi L x Cd m$ owz Hz mm i z E United States Patent O DIGITAL SYSTEMS FOR THE AUTOMATIC CONTROL OF MACHINERY Doran C. Hierath, Santa Monica, and Claude A. Lane,
Culver City, Calif., assignors to Hughes Aircraft Company, Culver City, Calif., a corporation of Delaware Application October 25, 1954, Serial No. 464,410
11 Claims. (Cl. 164-`115) This invention relates to digital systems for the automatic control of machinery and, more particularly, to an electronic control system including a digital computer wherein a sequence of Operations to be performed is controlled by a corresponding series of digitally coded instructions which may be recorded as a stored program on a medium such as magnetic tape, drum, or disc, or on punched tape or cards.
The term *instruction or digitally coded instruction as utilized herein is ldefined to mean a set of digital information which is properly coded for controlling a desired operation of a machine. The term "program is defined to mean two or more instructions arranged to be utilized serially, one at a time. The term stored program is defined to mean a program which has been recorded on a medium such as magnetic tape, drum, or disc, or on punched tape or cards.
A system has been proposezl in the prior art for the automatic control of machinery which may be referre'd to as the analogue play-back technique. According to this technique aseries of machine operations are perforrned under the control of a skilled mechanic or operator, the performance of the machine being recorded on a suitable medium so that the record may be played back in order to control the machine to repeat automatically thereafter the same performance. Such a system is described in U. S. Patent 2,475,245 entitled Method and Apparatus for the Automatic Control of Machinery, issued on July 5, 1949 to Eric W. Leaver et al. A similar system is described on pages 102 through 108 of an article entitled Tape-controlled machines by L. R. Peaslee. in Electrical Manufacturing November 1953. The analogue play-back technique has several distinct disadvantages. The accuracy of a system of this type is limited by the accuracy of the skilled mechanic as well as by the accuracy of the recorded analogue signals and of the devices controlled thereby. Finally, a skilled machine operator to prepare each program may not be readily available.
Prior art digital control systems have been described, for example, on pages 114 and 115 of an article entitled Digital computer controlled machine tool by E. D. Gittens, in Electrical Manufacturing August 1950, and on pages 133 through 137 of an article entitled Numerically controlled milling machine by A. K. Susskind et al., in the Review of Input and Output Equipment Used in Computing Systems, American Institute of Electrical Engineers, March 1953. A system of this type is also described in U. S. Patent 2,537,427 entitled Digital Servo by E. Seid etval., issued January 9, 1951. Each of these systems utilizes a complicated digital-to-analogue servo for translating the digital control information into analogue control signals which control, for example, a machine tool. For example, where the speed of a moving part is being controlled, an analogue signal is utilized to control the movement of the part in order to decrease speed in response to the analogue signal and as a predetermined function thereof as the desired stopping point "ice is approached. Thus, each of these systems is inherently very complex.
It is therefore apparent that, with any of the automatic control systems of the prior art, a direct digital control cannot be achieved.
Electronic digital control systems of the type disclosed by the present invention are particularly useful, for eX- ample, in controlling machine tool operations where one or more of the following features is desired: ease in programming different Operations; versatility; reliability in performing repeatedly the same operation; high degree of accuracy; and speed.
In accordance with the present invention, ease in programming a series of Operations arises from the fact that each independent operation may be specified by means of a separately digitally coded instruction. A program which consists of a series of separate Operations of a machine tool may therefore be prepared by an operator who has no particular knowledge of the machine tool itself.
The electronic digital control system provided by the present invention is highly versatile. Analogue data representing observed physical values such as, for example, the instantaneous position of a machine tool, or a part thereof, is converted directly at the source into digital data such as electro-nic pulses available for the computer. Digital data is, in turn, utilized directly in carrying out the control function, for example, in positioning the machine tool. Thus, the entire control system is designed to interpret measured data, and to carry out desired instru'ctio-ns, in accordance with the digital language of the computer. A machine to be controlled may therefore be' programmed for any series ofl cperations of which it is capable and a particular program may wlth equal ease be repeated indefinitely or interchanged with other programs.
Reliability in performing repetitive Operations is achieved because no human intervention is required while a' particular program is being carried out, hence no human errors are introduced into the operation. A further significant feature is that a particular program may be permanently stored on a medium such as magnetic tape and may be kept for any desired time and may then be utilized again without requiring a skilled operator.
The accuracy of a digital control system may be limited both by the accuracy of the devices to be contro'led thereby and also by the digital capacity of the system. According to the present invention, however, the control system has a digital capacity suflicient to provide greater accuracy than that inherent in the devices, hence the accuracy of the over-all system is limited only by that of the devices to be controlled.
l'n servo loop systems in general, there exists the problem of bringing the part to be moved to rest at a desired point; that is, the inerta of motion of the moving part must be overcome without introducing any oscillatory or '*hunting action, at the same time bringing the system to the proper point of rest in as short a time as possible. Whereas control systems of the prior art have controlled speed directly as an analogue function of the remaining distance to a desired stopping point, the digital control system of the present invention controls speed as a step function. Thus, for example, full speed may be utilized until a predetermined distance to the desired stopping point remains; a slow speed for the remaining distance; and at final destination, speed is reduced to zero and braking is employed.
One of the advantages of the system of the present invention lies in the use of an integrated program unit whereby the control circuits used for controlling machine Operations may also be employed for preparing and storflexibility inasmuch as the program may be readily modiasaasoe fied at any time to incorporate engineering changes, the only action which is necessary being to erase a particular portion frOrn the magnetic tape or ofher storage medium and to re-record the new instructions as desired.
In accordance with the present invention, the position control function is exercised in the following manner. A motion detecting and indicating device is mounted upon the movable part for producing, in direct response to the motion of the part, digital signals such as voltage pulses. An electronic counter, responsive 'to these digital 'signals or pulses, is utilized to maintain a continuous record in numerical or digital form indicating the instantaneous position of the part. Circuit means are provided for receiving and storing a digital number or count which represents the desired position of the movable part and for perfo-rming a continuous co'mparison between this desired position and the instantaneous actual position. When `the desired position is reached, an output signal is produced for controlling lother sub-Operations. The position control function may be accomplished either according to a relative address system or an absolute address system, as will be more specifically described, the mechanization of the circuits being largely determined by the speed control schedule of the -present invention, wherein the Velocity of the movable part is reduced in a stepwise manner as it nears the desired stopping point.
Accordingly, it is an object of the present invention to provide a system for the automatic control of machinery, wherein electronic digital control signals are utilized directly to control the desired function wi.h:ut the interventio-n of digital-to-analogue devices.
Another object of the invention is to provide a digital system for the automatic control of machinery or the like wherein ease of programming is attained' by utilizing a digitally coded instruction to specify each independent operation to be perfo-rmed.
A further object of the invention is to provide a digital control system wherein a series of Operations may be performed in accordance with a previously recorded program.
Yet a further object of the invention is to provide a digital electronic system for automatically positioning a machine tool wherein the Velocity of the tool is decreased in discrete steps as a desired position is approached.
Still another object of the invention is to provide a digital electronic system for automatically positioning a machine tool in accordance with a previously recorded program, the system including means for reccrding the program in the first instance or for re-recording selected portions of the program as may be required by engineering changes.
An additional object of the invention is to provide a versatile and accurate digital control system wherein errors incident to the positioning of a movable part in accordance with one operation have no cumulative effect upon the positio-ning of the part in` accordance with succeeding Operations.
Still a further object of the invention is to provide a digital electronic control system for automatically positioning a movable part in successive locations wherein each location is specified by means of a relative address indicating the distance from the previous location, an 'accumulation of errors being avoided by modifying each relative address in accordance With any error in the positioning of the part at the previous location.
Yet another object of the invention is to provide a digital electronic control system for automatically positioning a movable part at successive locations wherein each location is specified as an absolute quantity .with respect to a zero or origin point, a continuous and instantaneous reference being maintained, at all times, with respect to the Origin 'point and direct digital control signals being produced in response to a continuous comparison of the reference signal, representing instantane" ous actual location of the part, with the absolute quantity representing the desired location.
The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better unders-tood from the following description considered' in connection with the accompanylng drawings in which a -specific embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only, and are not intended as a definition of the lirnits of the invention.
Fig. 1 is a block diagram of a punching 'machine and a digital control system for automatically controlling it in 'accordance with the present invention;
Fig. 2 is a schematic diagram -of .the sequence 'control unit utilized in the system of Fig. 1;
Figs. 3a, 3b, and 3c are circuit diagrams of a flipfiop circuit and a flip-fiop resetcircuit suitable for use in the circuit of Fig. 2 and elsewhere throughout the system of Fig. 1;
Fig. 4 is a schematic diagram of a manual program' m'ing unit suitable for use in the system of Fig. l;
Fig. 5 is a block diagram of a program unit 'suitable for use in the system of Fig, 1;
Fig. 6 is a schematic diagram 'of a servo motor and of 'a logical circuit for 'controlling the same, suitable for use in the system of Fig. 1; I
Fig. 7 is a schematic diagram of a punch control circuit suitable for use in the system of Fig. 1;
Figs. 8a and 8b considered together are a schematic diagram of a punch address and comparison circuit, in accordance with the absolute address system of control, suitable for use in the system of Pig. 1;
Fig.` Sc is a schematic diagram, partly in block form, of a counter circuit suitable for use in 'the circuit of Figs. 8a-8b;
Fig. 9 is a schematic diagram of a punch address and comparison cir-cuit according to the rel-ative address method of control, suitable for use in Fig. l; and
Fig. 9a is a schematic diagram of a counter circuit suitable for use in the circuit of Fig. 9.
THE SYSTEM Reference is now made to Fig. 1 wherein there is shown a system in accordance with the present invention for automatically controlling a punching machine by means of an electronic digital computer. The system of Fig. 1 co-mprises positioning control and detection apparatus 200; punch control and detection apparatus 210; computer programming and control circuits 220, all indi- 'cated generally by dotted rectangles; and a manual programming unit 230. A brief description of each of these major portions of the system will now 'be given.
Included within positioning control and detection apparatus 200 are separate X and Y carriages for supporting and positioning fiat-work W to be punched. The carriages may be moved to provide any desired position of the work within a plane X--Y coordinate system by means of servomotors MSX and Y, which are controllable through X and Y motion control circuits X and 150Y, respectively. X and Y motion detectors x and 160Y cooperating with the respective carriages detect the motion thereof or the distance traveled from a starting point and produce corresponding electrical digital signals such as voltage pulses which are then supplied to the computer circuits.
The punch control and detection apparatus 210 includes a punch control circuit 170, a punching mechanism 180, and a punch-done device 19,0. The punching mechanism is located in a fixed position above the work. Punch control circuit actuates the punching mechanism in response to signals generated by the computer when the carriagesreach' a desired posi tion. Upon the tipward or` eturn stroke of the punching mechanism, device 190 is actuated for producing a digital electrical signal which is supplied to the computer to indicate that a punch has been completed.
Computer programming and control circuits 220, hereafter referred to as the computer, include a program unit 100, a Y punch address and comparison circuit 130Y, and X punch address and comparison circuit 130X, and a sequence control unit 110. Program unit 100 is adapted to contain a stored program consisting of a series of separate instructions of a fixed length. The program may, for example, be stored by a magnetic tape included in the program unit. Each of the punch address and comparison circuits 130X and 130Y includes a static storage register (not shown) for receiving portions of the instruction respectively representing X and Y addresses of a desired punch location. The punch address and comparison circuits are also adapted to exercise control over the X and Y motion control circuits 150X and 150Y when an instruction is being carried out. Sequence control unit 110 includes means for controlling four major Operating phases, as will now be explained.
Manual programming unit 230 is utilized in one of the major Operating phases for the advance preparation of a program. This unit includes manual controls for setting the static storage portions of the X and Y punch address and comparison circuits to correspond to a desired instruction. In this manner, an entire program may be prepared, one instruction at a time, directly from drawings by an operator who need not be familiar with the workings of the punching machine itself. The manual controls may also be conveniently utilized for re-recording a portion of a program to conform to engineering changes, for example.
Within sequence control unit 110 two binary or onolf control signals Rz* and St (not shown) having the value 0 or 1 are utilized to represent the four major Operating phases. These operating phases and the signals which represent; them may be conveniently tabulated as follows:
Table l As will be apparent from Table I the manual programming unit is utilized only during phase I for setting up an instruction, whereas positoning control and detection apparatus 200 and punching control and detection apparatus 210 are utilized only during phase IV for the performance of an instruction. Phases II and III, therefore, take place entirely within the computer.
Sequence control unit 110 includes manual controls for setting the signals Rt and St to 0 or to 1 whereby an operator may conveniently switch the operation of the system from one phase to another. During program performance, however, it is desirable for the operation to be carried out continuously, hence the sequence control unit also includes meansl for automatically switching back and forth between phases III and IV.
Before considering the structure and function of speific components of the system of Fig. 1 it will be advantageo-us to describe the operation of the system as a whole. This description of operation may be conveniently organized upon the basis of the phases established in Table I.
' During phase I the manualprogramming unit is uti- 6, lized for setting up a desired instruction. The static storage register of each of the punch address and comparison circuits comprises a bank of flip-fiops or b1stable circuits, each capable of storing a binary digit, according to the state to which it has been set. Thus, a serles of 1s and 0`s representing the Y punch address is set into circuit 130Y and a similar series representing the X punch address is set into circuit 130X. A single flipflop RC (not shown) in sequence control unit 110 is set to a l-representing state corresponding to a marker bit, aswill be explained. When the instruction is complete, the signal St of the sequence control unit is manually set to 1 to initate phase II.
During phase II the instruction is transferred from the static storage registers of the punch address and comparison circuits and from flip-fiop RC serially into program unit 100. In Fig. 1 the arrows designated I indicate the flow of information from Y punch address circuit 130Y to X punch address circuit 130X, from X punch address circuit 130X to sequence control unit 110, and from sequence control unit 110 to program` unit 100. Thus, the marker bit previously stored in fiip-fiop RC becomes the first bit of the instruction to be recorded in the program unit.
Separate instructions may thus be set up and recorded on the tape as desired until a complete program has been prepared. This stored program may then be utilized for punching a piece of fiat work in one continuous operation, or for punching a quantity of pieces in a repetitive operation as may be desired.
During phase III an instruction is serially transferred from the program unit (as indicated by arrows I) into Y punch address circuit 130Y and hence into X punch address circuit 130X and into flip-flop RC. The arrival of the marker bit in flip-flop RC denotes the completion of the instruction transfer, and changes signal St from 1 to 0, thus initiating phase IV.
Throughout all the Operating phases program unit 100 is Controlled by means of signals Rt and St from the sequence control unit, these signals being jointly designated in Fig. l
' by an arrow Seq. Another arrow, Rc, originating from the sequence control unit indicates the application of the output signal of fiip-flop RC to circuits X and 130Y for controlling their operation during phases III and IV in a manner which will be more apparent from the detailed description of those circuits.
During phase IV operation the X and Y carriages are moved to their desired locations under the supervisory control of address and comparison circuits 130X and 130Y with the assistance of digital motion signals Px and Py supplied by motion detectors X and 160Y, respectively. When an instruction is being transferred into the control circuits during phase III operation the carriages remain at rest in the punch position corresponding to the previous instruction; in response to the new instruction the carriages are then moved directly to the desired new location. In performing an instruction each carriage is moved initially at full speed; speed is decreased to approximately half at a predetermined distance of the carriage from its new position; and the carriage is stopped when it reaches its destination. When both carriages have stopped, punch control circuit Supplies a signal Pc for actuating the punching mechanism, and after completion of the punch a signal Do is supplied by device for resetting the control circuits to receive the next instruction and for switching signal St to 1 in order to again initate phase III.
The system of Fig. 1 provides a high speed operation of reasonable accuracy, in order to achieve production economy, rather than the greatest possible accuracy with correspondingly slower Operating speed and more expensive equipment. Thus, where, for example, holes are to be punched in a work piece 4" x 4 and the assumed..
maximum accuracy of the system is 0.001 inch or 1 mil,
an error of greater than 1 mil in locatingv each punch position may nevertheless be permitted to occur. For example, the inertia of the relatively heavy carriage mechanisms may produce an over-travel of as much as 3 mils. According to the system of Fig. 1, any such error as detected by motion detectors 160X and MY, is duly registered in the punch address and comparison circuits, and is taken into account within the punch address and comparison circuits in positoning the carriages at the next punch location.
Motion detectors 160X and 160Y which are not specifically shown and described herein, may be of the type described and claimed in copending patent application Serial No. 402,263 for Gated Light Pulse Generating Mechanisrn for MeasuringMotiom by Doran C. Hierath, filed January 5, 1954 and now abandoned. The detector therein described utilizes two optical gratings, each having lines scribed thereon at a predetermined spacing, relative motion between the two gratings being detected photoelectrically. The complete detector unit includes electrical output means for producing a discrete pulse signal whenever a predetermined relative displacement between the two gratings has taken place. One grating may, of course, be permanently fastened to the particular carriage to move therewith, while the other grating is fastened to the fixed frame of the punching machine. In accordance with the system of Fig. 1 the predetermined displacement is 1 mil. Thus, each motion detector produces one pulse on the completion of each 1 mil of travel by the corresponding carriage. These digital signals or pulses designated as Px and Py; are transmitted from the motio-n detectors to the respective punch address and comparison circuits.
During phases II and III the shifting of instructions through circuits 130Y, 130X and fiip-fiop RC of circuit 110 requires ti'ming or synchronization. This is provided by clock pulses which are generated within program unit 100 and which are designated in Fig. 1 by means of arrows Cp. During carriage motion the digital motion signals Px and Py are utilized for synchronizing counting operations and other control functions of circuits 13032 and 130Y, respectively. Thus, during phases II and III the two punch address and comparison circuits are synchronized with each other and with the program unit; during phase IV, however, each is separately synchronized with the motion of the carriage which it controls.
It is convenient to employ bistable flip-hop circuits throughout the system of Fig. 1 for producing and storing various binary or on-off control signals. Accordingly, voltage-state signals of the type produced by flp-flop circuits, as distinguished from pulse signals, will be assumed throughout the discussion except where other- Wise noted. A binary variable such as A may be represented by means of a pair of complementary electrical signals denoted as A and respectively. Signal A may then be regarded as a primary electrical signal which directly represents the binary variable A, whereas signal is a complementary signal which has a O-representing value when A is 1, and a l-representing value when A is 0. This method of representation, which is now well known in the art, provides advantages in the mechanization of logical circuits as will become more apparent from the detailed description.
Other control signals indicated in Pig. 1 are utilized during phase IV and are assigned conventional meanings corresponding to l-reprcsenting values as follows:
Op-Phase IV operation Sx-Positive motion of X carriage J- Negative motion of X carriage Mx-Motion in X drection is desired lvlx- Motion in X drection isnot desired Mxr-Speed of X carriage is to be reduced S- Positive motion ofY carriage a''-Negative motion of X carriage 8 Myt-Motion in Y drection is desired /-Motion in Y drection is not desired Myr-Speed of Y carriage is to be reduced Most of the circuits which are utilized to provide the direct-digital control signals, in accordance with the baslc principles of the present invention, are mechanized according to logical equations. Although in the discussion which follows there will be described specific embodiments of circuits which may be utilized in the system of Fig. l, it must nevertheless be understood that each such logical Circuit has, in general, a number of equivalents which while differing in detail accomplish the same result. Accordingly, emphasis will be placed upon the functional concept associated with each such circuit, and the logical derivation of the various control signals and of the circuits for mechanizing them will be explained.
The principles of' logical or Boolean algebra will be frequently employed in this discussion and will be utilized for mechanizing the circuits directly by means of and and or gates which correspond directly to the logical equations. It is not considered necessary to describe the specific mechanization of the '*and and or circuits since these circuits are well-known in the art. Typical circuits are shown, for example, on pages 37 to 45 of High-Speed Computing Devices by Engineering` Research Associates, published in 1950 by McGraw-I-Iill Book Company, Inc., New York and London, and on pages 511 through 514 of an article entitled Diode coincidence and mixing circuits in digital Computers by Tung Chang Chen, in the Proceedings of the Institute of Radio Engineers, volume 38, May 1950.
SEQUENCE CONTROL UNIT Reference is' now made to Fig. 2 wherein there is shown a schematic diagram of the sequence control unit in accordance with the present invention. The sequence control unit produces binary signals Rt, St and Op, as previously explained, and also includes the flipflop RC which is coupled into the information channel I shown in Fig. 1.
In accordance with the utilization of a marker bit at the beginning of each instruction as previously explained, and in order to provide automatic switching back and forth between phases III and IV when a program is being performed, the Operating phases are represented by signals Rt, St, and Rc as follows:
Table II Phase Rt Thus the arrival of a marker bit in flip-flop RC changes its output signal Rc indicated in Fig. 2 from 0 to 1 initiating switching from phase III to phase IV. Similarly the resetting of flip-flop RC to 0 by signal Do from device at the end of phase IV initiates switching back to phase III.
The corresponding mechanizations are illustrated in Pig. 2. Signal Rt is produced by a manually Controlled double-pole double-throw switch whereby a pair of complementary electrical signals Rt and Rt may be provided by selectively connecting the two o-utput terminals of the switch either to ground and to a voltage source B-[-, or vice versa.
In order to initiate phase II, for the recording of an instruction, signal St may be set to 1 by manually depressing a start button as illustrated. The start button actuates a timing network which produces a high-level output voltage signal for a predetermined period of time upon being energizedby a voltage source B+ through the start button. The purpose of, the timing network is to operate the magnetic tape only for a sufficiently long time to record an instruction and to permit a short space on the tape between instructions.
Signal St must also be set to 1, as indicated in Table II, when Rt is 1 and Rc is 0. The complete expression for the l-representing value of signal St is therefore where the dot represents the logical and function and the plus represents the logical or function.
Accordingly in Fig. 2 there is included an '*and circuit 111 having two separate input terminals to which signals Rt and c' are applied, and an output terminal; and an "or" circuit 112 having two separate input terminals, one of which is connected to the manually operable timing network, and the other of which is connected to the output terminal of the'and circuit 111. The or circuit 112 has an output terminal upon which signal St appears. Each 'and circuit is represented by means of a semicircle containing a dot and each "or circuit is represented by means of a semicircle containing a plus such circuits being, as previously explained, so well known in the art as not to require illustration in greater detail.
Signal Op representative of phase IV may, from Table II, be provided as follows:
where the dot represents again the logical and. Accordingly in the circuit ofFig. 2 there is included an and circuit 113 having two separate input terminals to which signals Rt and Rc are applied, and a single output terminal providing the function Op, which has a l-representng value whenever both signals Rt Esand Rc have 1- representing values.
Signals Rz, R-t, and St, designated jointly as Seq, are supplied to program unit 100 for sequence control purposes.
The output signals Rc and Rc from Vflip-flop RC are supplied during phase II to program unit 100 as information signals; and are also supplied to address and comparison circuits 130X and 130Y for controlling shifting Operations therein in a manner which will be explained in connection with Figs. 8 and 9.
During the shifting of instructions (phases II and III) flip-fiop RC receives information signals from a flip-fiop in X punch address circuit 130X (either flip-flop MXR of Fig. 8 for absolute address system, or flip-flop X2m0 of Fig. 9 for relative address system). These input functions for flip-flop RC may then be specified as:
FLIP-FLOP AND RESET CIRCUITS Reference is now made to Figs. 3a, 3b, and 3c, showing in detail a suitable mechanization of flip-flop RC and of a special reset circuit for controlling the fiip-flop. Fig. 3a illustrates the fiip-flop and the reset circuit in block form; Fig. 3b shows a schematic circuit diagram of the reset circuit; and Fig. 3a is a schematic circuit diagram of the' In Fig. 3a fiip-fiop RC is indicated in having J and K inputs as well as two output circuits providing primary and complementary output signals blockform as Rc and RE, respectively. In addition, fiip-flop RC is shown as having a special O-Setting input circuit Ka. A reset circuit Ka(N) shown in dotted lines generates a reset signal for controlling the Ka input of flip-flop RC as Well as the Ka input circuits of other fiip-fiops in circuits 130X and 130Y, as will be explained. Circuit Ka(N) includes an or circuit for controlling a cathode follower CF in response to signals Reo and Do in a manner which will be described.
Reset circuit Ka(N) is illustrated in detail in Fig. 3b, Wherein a battery Ec represents a source of biasing voltage normally applied to the grid of cathode follower CF. "Or gate 115 is selectively responsive to either signal Rea or signal Do for making the grid potential of the cathode follower more positive, thus selectively supplying a positive bias over and above the normal bias supplied to the cathode follower. The output signal from the cathode of the cathode follower is appliedpto the Ka input of flip-flop RC, and is also available to circuits X and 130Y as indicated by the' arrow marked Re0+D0.
Fig. 3c shows the flip-flop circuit in detail, including major portions thereof respectively indicated by dotted lines F, J, K, Ja, and Ka. Circuit F is a bistable trigger circuit of the Eccles-Jordan type including a pair of crosscoupled triodes, and further including a clamping network whereby one of the output signals Rc and Rc is maintained at one voltage level and the other output signal at another voltage level, the two voltage levels being specifically indicated as zero volts and -20 volts. Input circuits J and K may include, in addition to the conventional circuit shown, a gating circuit of the type described in copending patent application Serial No. 327,133 for *Diode, Pulse-Geting Circ'uits by Richard D. Forrest, filed December 20, 1952 and now Patent No. 2,762,936. The gating circuit described in the copending application is particularly suitable for logically combining voltage-level signals With pulse signals, and more specifically, for selectively passing a negative clock-pulse when an associated voltage-level signal is at the higher one of its two possible levels.
Input circuits Ja and Ka each consists of a single diode which may, as described in copending application Serial No. 443,741 for Electronic Flip-Flop Circuits, by Cameron B. Forrest, filed July 16, 1954, be biased at a fixed potential which is below cutoff by the expected noise level, for improving the trigger sensitivity of the flip-fiop circuit. However, by taking the bias from reset circuit Ka(N) the single diode performs this type of clamping function when the no-rmal bias is applied, and controls the conduction state of the flip-fiop when a more positive bias is applied. More specifically, the application of a more positive bias to the Ka input resets the flip-fiop to an (l-representing state in which the primary output signal Rc is at the O-representing or lower voltage level of 20 volts and the complementary output signal R2' is at the l-representing or higher voltage' level of zero volts; and the application of a more positive bias to the Ja input resets the flip-fiop to a l-representng state.
a Reset circuit Ka(N) and the Ja and Ka input circuits need not be described in greater detail herein inasmuch as they are the subject of copending patent application Serial No. 484,667, Voltage State Reset Gate, by Claude A. Lane, filed January 28, 1955. It should 'be pointed out, however, that the use of thel special reset circuit and of the Ja and Ka input circuits for automatically resetting Various flip-flops in accordance with the present invention may be obviated by employing more complex logical gating circuits for controlling the conventional 1 and 0 input circuits of the various flip-flops. The flip-flop circuit of Pig. 3c also includes a pair of buttons for manually resetting the flip-flop to the 1 orv 0 state as desired. A black button may be manual- 11 ly depressed for directly connectng the primary output signal Rc to the lower voltage source of 20 volts, thus setting the fiip-fiop to the or off condition; whereas' a' red button is similarly operable for setting the flip-flop to the 1 or on condition. These buttons are physically located in the manual programming unit.
MANUAL PROGRAMMING UNIT Reference is now made to Fig. 4 showing the structure of manual programming unit 230 in detail. A single switch 231 is provided for supplying the reset signal Reo which, through the medium of special reset circuit KMN)v as previously explained, is utilized for simultaneously setting various flip-flops of the system of Fig. 1 to their 0 state.
In addition, a plurality of pairs of button switches are provided for separately setting the various fiip-flops to 0 or l as vdesired. For example, button 232 is the black button for setting flip-fiop RC to 0, and is operable to connect to a source of 20 volts an output lead designated R'c-O, which is connected to the primary output circuit of flip-flop RC as previously described. Similarly, a red button 233 and output lead Rcl are included for s-etting fiip-flop RC to 1 in the manner previously explained.
The various output leads designated as going to circuits 1'30X and 130Y are labeled in accordance with flip-flop designations employed in the absolute address system of Fig. 8. It will of course be understood that for utilization with the relative address system of Fig. 9 the structure and function of the programming unit are substantially the same -eXcept that the signals provided by the various output leads are applied to different flip-flops.
PROGRAM UNIT Reference is now made to Fig. wherein there is shown in block diagram form a magnetic tape storage unit which is suitable for use as the program unit 100 of Fig. l. Storage or program unit 100 includes a twochannel tape 101, a motor 102 for operating the tape, and various reading and writing circuits as will be explained.
The tape includes an information channel I upon which instructions may be recorded through a writing flip-flop WT and a writing head during phase II operations, or from which instructions may be read by means of a reading head and a reading fiip-'lop RD during phase III Operations. The second tape channel Cp has timing or clock pulses Cp permanently recorded thereon, which are continuously read by a pick-up head during phases II and III and are made available through a blocking oscillator E0 for timing or synchronizing purposes. The blocking oscillator is gated on by a gate 103 in response to signal St.
The operation of storage unit 100 is Controlled by signals St, Rr, and Rt received from sequence control unit 110. Thus, signal St is applied to a motor control circuit for Operating the tape whenever St is 1, namely, during phases II and III. Signal St therefore has the logical meaning of start tape In a similar manner signal Rt, which has the logical significance read from tape, is likewise utilized to control flip-fiop WT to perform writing Operations during phase II. Information represented by signals Rc and RE is gated into the flipflop under control of the function ICp, which represents phase II since the clock pulses are available only when St is l (see Table I or Table II). Thus in Fig. 5 flip-fiop WT is Controlled according to the functions lt is apparent that a program unit of the type shown in Fig. 5 is small, compact, and economical, and therefore greatly enhances the utilityv of the system of Fig. 1.
The tape may be started or stopped at the convenience. of the operator since signal St may be manually controlled. An engineering change, for example, may therefore be incorporat'edi into a program merely by rerecordingV one or more of the instructions included therein.
Durng phase III output information is generated byV fiip-flop RD under the control of a gate 104, according to the function Rt.Cp, the` clock pulses again having the same logical significance as signal St. Output signals Rd and are supplied to circuit Y.
VFrom the above description of the program unit the advantage of. the marker bit and of the use of flip-flop RC becomes more apparent. Timing within phase III is provided by clock pulses Cp, and timing within phase IV by digital motion signals Px and Py,` whereas the marker bit and flip-flop RC perform the transitional timing functions in changing from one phase of operation to the other.
The magnetic tape storage unit of Fig. 5 has been shown and described generally, rather than specifically, since such systems are very Well known in the art and the particular details thereof form no significant part of the present invention. Program unit 100 may, however, be a data storage system of the general type shown and described in U. S. Patent 2,540-,654 entitled Data Storage System, issued on February 6, 1951, to A. A. Cohen et al. The above patent describes a magnetic drum memory or storage system wherein one channel is employed as a timing track upon which timing pulses are permanently recorded, and another channel isV employed asV the program or information channel. of this general type, the timing pulses may be utilized for synchronizing related circuits during an information read-in or recording phase of operation, and also during,
an information play-back or read-out phase of operation.
MOTOR AND cIRcUrr FOR corrrRoLLINGH CARRIAGE MOTION Referring now to Fig. 6 there is shown a servo motor 1-45X and a motion control circuit 150X for controlling the operation thereof, both being identified by dotted rectangles.
Motion control circuit 150X is operative during phase IV (indicated by signal Gp) to provide X carriage mon tion controllecl' by signal Mx) either in the positive or negative direction (Controlled by signals Sx and Sx, respectively) either at full speed or a reduced speed (controlled by signal Mxr.). These signals are accordingly supplied as the input signals for circuit 150X.
Although servomotor x may be of any desired type, the type illustrated in Fig. 6 is a clutch-Controlled motor having both a positive clutch 147X and a negative clutch 148x which can be separately actuated to provide full speed in either directio-n, or which can be actuated in combination to provide a reduced speed in either direction by having one clutch on and the other clutch half on. Thus, full speed in the positive directon may be provided by supplying a full clutching current to clutchl 147x, whereas a reduced speed is achieved by simultaneously supplying a full clutching current to clutch 147x and a reduced clutching current to clutch` 148X. Motor 145X includes a series resistor 146x which causes the speed to fall with increased load so that the loading effect of applying both clutches .also results in a reduced motor speed. It will be understood, of course, that motor 145X may be selected to have the proper speed-load characteristic so that resistor 146Xv may be .unnecessary Clutches. 147X and 148X may be magnetic clutches of any desired type.
Within circuit 150X there are a pair of amplifiers 151x and 152X for supplying full clutching currents to clutches 147x and 148X respectively, and also a second pair of amplifiers 153X and 154X for supplying reducedv With. asystem 13 currents to clutches 147X and 148X, respectively. Full speed of the carriage in the positive direction, for example, is therefore achieved byenergizing amplifier 151X only, whereas reduced speed is achieved by also energizing amplifier 154X. Each of the four amplifiers may be a direct current amplifier responsive to an input signal of predetermined magnitude' for supplying a predetermined output current.
The various carriage speeds and the respective signals produced within circuit 150X for controlling them may be conveniently tabulated as follows:
Each of the above digital motion control signals may be an on-o signal and may be expressed as a logical "and function in terms of the input signals supplied to circuit 150X. Thus, the signal Mic may be defined as having a l-representing value when signal Op is 1, indicating phase IV; when signal Mx is l, indicating that motion of the X carriage is desired; and when signal Sx is 1, indicating motion in the positive X direction. This relationship may be expressed by the following equation:
In a similar manner the other control signals may be expressed by equations as follows:
In Fig. 6 the function Op.Mx is provi-ded by an 'and circuit 155X and is supplied both to and circuit 156X and *and circuit 157X where it is combined with signals Sx and Sx for producing the functions Mx and Mx, respectively. A cathode follower buifer stage 156XB is interposed between and circuit 156X and the utilization circuits to which signal Mx is applied, including amplfier 151X and an *and circuit 159X for producing signal Mic r. The mechanization of the remainder of circuit 150X is readily apparent from the above equations.
It will be noted that when the carriage reaches its desired location, signal Mx changes from 1 to 0, thus changing both signals Mx and Mxr to and simultaneously deenergizing both of the magnetic clutches.
It is not necessary to describe servo motor 145Y and motion control circuit 150Y since their structure and function are identical to those of servo motor 145X and circuit 150X, respectively. For example, circuit 150Y is responsive to signals Op, Sy, My, Sy, and Myr for producing control signals My, My, My r, and Myr.
Eflicient control of carriage position may also be provided by ultizing a closed hydraulic system in lieu of the pair of magnetic clutche's described above. A carriage-actuating cylinder and piston may be provided having a separate oil chamber in each end, the output signal of each amplifier being then applied to control the entry of oil into the respective chamber.
14 PUNCH CONTROL CIRCUIT Reference is now made to Fig. 7 which shows in diagrammatic form punch control circuit 170 of Fig. 1. Punching is to be perforrned during phase IV after both of the X and Y motion control signals Mx and My have gone to' 0, hence the expression:
where signal Op is the "and function RLRC as explained in connection with Fig. 2. Accordingly, Fig. 7 illustrates a three-terminal and circuit to which the signals Op from sequence unit 110, Mx, and My from the X and Y punch address circuits are applied and which produces an output signal Pc having a l-representing value when all of the input signals have l-representing values.
It is not deemed necessary to show or describe in detail the'apparatus within punching mechanism 180 for actuating the punching mechanism in response to a 1- representing value of signal Pc, since controls of this type are very well' known in the art.
ABSOLUTE ADDRESS SYSTEM Reference is now made to Figs. 8a, 8b and Sc wherein there is illustrated in schematic form the structure of punch address and comparison circuit 130X in accordance with an absolute address method of control. Figs. 8a and 8b considered together illustrate the entire circuit whereas Fig. Sc illustrates in greater detail an updown absolute reference counter suitable for use in the circuit of Figs. 8a-8b. It will be convenient to discuss briefiy the general theory of operation before describing the circuits in detail.
According to the absolute address method of control each address is specified with respect to an origin or reference position, for example, each punch location may be specified by means of two absolute numbers corresponding directly to its X and Y coordinates, respectively. It is therefore necessary for each of the X and Y punch address and comparison circuits to receive and store a first set of information corresponding to a desired carriage position and a second set of information corresponding to the instantaneous actual position, and to perform a comparison for the purpose of stopping the carriage when the two information sets are identical. According to the present invention the first set of information is provided by the program unit and is stored in a static storage register whereas the second set vof information is provided by digital motion pulses actuating an absolute reference counter to count either up or down as necessary in order to continuously maintain a count representative of the actual carriage position.
It is, in general, necessary to specify separately each carriage position where any action is to occur. For example, in order to provide reduced carriage speed for a predetermined distance prior to the stopping point it is necessary to separately specify a reduced-speed location and a stopping location. It is also necessary to specify in the instruction whether or not any carriage motion is desred, the direction of carriage motion, and whether carriage motion is to be initiated at full speed.
Accordingly, a complete X address may include an X reduced-speed address, an X stop address, and various motion control signals such as Mx, Sx, and Mxr. The instruction then includes a marker bit, a complete X address, and a complete Y address, and in accordance with the control system described herein the entire instruction is arranged to form a single series.
In its general form, therefore, the circuit of Figs. Sa-Sb includes a static storage register 131X for receiving and storing a complete X address; an4 absolute reference counter 132X responsive to motion pulses Px for continuously representing the actual location of the X carriage; a reduced-speed comparison circuit 133X for producing a comparison signal Cxr at the reduced-'speed assasoe 195 location; and a stopping point comparison circuit 134X for producingv a signal Cxs at the desired carriage position; each being enclosed by dotted lines.
During phase III a complete X address is transferred into static storage register 131X, the information transfer being synchronized by means of Aclock pulses Cp from program unit 100. During phase IV the absolute reference counter 132X is responsive to motion pulses Px produced by motion detector 160X to count either up or down according to the direction of carriage travel as indicated by sign digit Sx. Most of the complete X address is maintained in static storage by register 131X throughout phase IV when a particular instruction is being performed; however, motion control signals Mxr and Mx may change their values during the performance of an instruction in response to comparison signals Cxr and Cxs, respectively, as will be explained.
In the circuit of Figs. 8a-8b a variety of codes are possible for specifying addresses and for the counting operation' of the absolute reference counter 132X. According to the circuit specifically shown, however, all addresses and counts are specified in the straight binary code wherein each binary digit is given a weight o-f 2n 1, where n corresponds to the digital place of the particular bit. The mechanization of the circuit of Figs. Sri-8b is also based upon the assumption that a Work piece 8 x 8 is to be punched and that each motion detector develops an output pulse in response to carriage travel in increments of 1 mil.
Thus storage register 131X includes a primary bank of 13 flip-flops Xfl, Xrz, X1'4, Xr4096 having a capacity equal to the decimal number 8191; and a secondary bank of 7 flip-fiops XS1, Xsz, X, X564 having a capacity equal to the decimal number 127. The absolute reference counter also includes 13 fiip-flops X1,X2, X4095 providing a total 'count capacity of 8191.
The primary bank of flip-flops in storage register 131X is utilized for receiving and storing a primary address representing the carriage location at which reduced speed is to be commenced, and the secondary bank of flipfiops receives and stores a secondary address representing the desired carriage stopping point. An economy of flipfiops for representing the secondary address is achieved by virtue of the fact that the Stepping-point comparison signal Cxs developed by comparison circuit 134x may be made dependent upon and may be produced as a function of the previously produced reduced-speed comparison signal Cxr, as will be explained hereinafter.
Static storage register 131X also includes motion control flip-flops MX, SX, and MXR, utilized for storing motion control signals Mx, Sx, and Mxr, respectively, received from program unit 180 as part of the X address. Signal Sx included in the original instruction is either 1 or according to the desired direction of carriage travel, and is stored in flip-flop SX throughout phase IV `until signal Do is produced. Signals Mx and Mxr change during phase IV, hence it will be convenient to utilize the following table to indicate the sequence in which the changes occur.
Table IV indicates that signals Mxr and Mx included in the original instruction have values of 0 and l, respectively. When the reduced-speed comparison signal Cxr is produced, signal Mxr is changed to 1 and when the stop comparison signal Cxs is produced, signal Mx 'is changed to 0. After completion of the punch the reset signal Do is operative to change signal Mxr to 0.
It is therefore apparent that a stopping point comparisonis desired only if signal Mxr stored in flipfiop MXR is l by virtue of reduced-speed comparison signal Cxr having been previously produced. The capacity of the secondary blank of fiip-fiops in the storage register need only be sufficient to represent the amount of reducedspeed travel which may be desired, and in the circuit of Pig. 8 is adequate to permit a maximum reduced-speed carriage travel of 127 counts or 127 mils. A numerical example will be helpful at this point to illustrate the comparison Operations more clearly.
Let it be assumed that the desired X address is 475, corresponding to 475 mils from the reference point, and that it is desired to provide reduced speed for the last mils of carriage travel. The complete primary and secondary addresses Will then appear as follows.
Table V.-Independent address By making the stopping comparison dependent upon a Table Vl.-Dependent addresses It will be noted that the abbreviated stop address of Table VI actually represents the decimal value 91. This value will appear in the least significant 7 bits in counter 132X at counts of 91, 219, 347, 475, 603, 731. The comparison signal Cxs cannot be produced at counts of 91, 219, or 347, however, as signal Mxr is still 0, but when signal Mxr becomes 1 imniediately after count 375 it then becomes possible for comparison signal Cxs to be produced at count 475, thus stopping the motion of the X carriage.
In some instances the total amount of carriage travel equired during the performance of an instruction may be small enough so that it is desirable to initiate the carriage motion at reduced speed, rather than at full speed. In such case signal Mxi' included in the instruction has the initial value of 1, Table IV being applicable as in the usual situation exccpt that the first step of the sequence is omitted.
The comparison function for producing signals Cxs, and which represents the structure of circuit 134X, may therefore be Written as follows:
It will be noted that 'signal Rc is also included in the above comparison function. The reason for this is that during the shifting in of an instruction in phase III, prior to the arrival of the marker bit in flip-fiop RC, it would otherwise be possible for a spurious comparison signal to be produced.
Signal Cxs must set motion signal Mx to 0. Flipfiop MX has a Ka input of the type described in connection with Figs. 3a and 3a, hence it is convenient to apply signal Cxs to the Ka input. The use of the Ka rather' than the K input is necessary because clock pulses Cp are not. .available during phase IV, and it is undesirable to utilize the next motion signal Px produced fromV motion of the X carriage since this would necessarily involve over-travel beyond the desired stopping point. As expla'ined in connection with Figs. 3a and 3c the K input is pulsed only upon the occurrence of a clock pulse (the equivalent of which during phase IV is the motion signal Px).
In a similar manner the comparison function for producing reduced-speed signal Cxr, and which represents the structure of circuit 133X, may be defined as follows:
Signal Rc is included as an 'and condition in the function for Cxr for the same reason that it is required in the function for Cxs. Since signal Cxr must change signal Mxr from 0.to 1, it is applied to the Ja input of flip-flop MXR, which is of the type described in connection with Figs. 3a and 3c, having J, K, Ja, and Ka inputs.
From the preceding discussion it is apparent that each instruction must include the primary address, the secondary address, and the initial values of motion control signals Mx, Sx, and Mxr. A typical instruction corresponding to the example set forth above, and to the additional assumption that carriage motion is in the positive direction, would then appear as follows:
It will be noted that in the circuit of Fig. 8 motion control flip-flops MX, SX, and MXR and address storage register 131X comprise a continuous shifting register, suitable for shifting an instruction to the left through flipflop RC of sequence unit 110 and hence into the program unit 100 during phase II and for shifting to the left an incoming instruction which is received from the program unit through circuit 130Y during 'phase III. The 1 and input circuits of ip-flop Xsl are therefore coupled to the corresponding output circuits of a flip-flop MYR provided in circuit 130Y, and the primary and secondary output circuits of flip-flop MXR are coupled to the corresponding input circuits of flip-flop RC in sequence control unit 110. I I
A complete instruction includes not only ,the VX addresses and motion signals as indicated above, but also the necessary Y addresses and motion control signals plus a marker bit. Assuming that the Y stopping point is 675, the reduced-speed point is 575, and that the carriage is to travel in the positive direction, the complete instruction in serial form as generated by the program unit is as follows:
COMPLETE INSTRUCTION 0100011 represents the Y stop address. Thus, the entire instruction contains 47 bits, including the marker bit andl 23 bits each for the complete X and Y addresses.
A common reset circuit is provided for allof the fiipfiops of address storage register '131X except flip-flop MX. Resetting of all of these flip-flops to 0 is accomplished either at the end of phase IV in response to signal' 'Do .or in response to signal Reo controlled by the operator. Accordingly, the output signal from circuit Ka(N) in sequence control unit 110, previously described in connection with Fig. 3 is utilized. It may be noted that the application of reset signal Do to fiip-flop MX is not required since as previously indicated in Table IV flip-flop MX is already set to 0 in response to signal Cxs. Signals Do and Reo are therefore combined as an or" function in a reset circuit Ka(MX) for controlling the Ka input of flip-flop MX.
As indicated previously in the descriptions of Figs. 1 and 6 circuit X supplies signals Mx, Mxr, Sx, and to circuit X for controlling the motion of the X carriage. Signal m is supplied to circuit ('Fig. 7) for actuating the punching mechanism.
Absolute reference counter 132X is responsive to carriage motion pulses Px from X motion detector 160X to count up or down as necessary in order to continuously maintain a count representing' instantaneous carriage position. Sign signals'Sx and produced by flipflop SX in register 131X are utilized for controlling the counting direction, with counting up being performed in response to Sx.Px and counting down being performed in response to JPx.
Reference is now made to Fig. Sevwhich illustrates several stages of a counter circuit suitable for use as counter 132X of Figs. 8a-8b. The circuit of Fig. 8c shows a simple binary cascade counter wherein motion signals Px from X motion detector 160X are applied to both input circuits of the first flip-flop X1 for continuously triggering it.
Each succeeding counting stage X0, is coupled to the preceding stage by means of a carry circuit Cx responsive to signal Sx for counting up and to signal Sx for counting down. The first carry circuit C1x is shown in specific detail and the other carry circuits are shown as symbolic 'and circuits.
Carry circuit C1x receives signals X1 and -'produced by flip-flop X1 and applied to separate input terminals 10 and 20. Terminal 10 is connected to one input terminal of a first pulse-and circuit Clxl and terminal 20 is connected to a similar input terminal of a second pulse-and circuit C1,, Z. Pulse-and circuit Cl-l i's operative to' produce a negative output pulse on leads 30 and 40 actuating the next'flip-flop stage X2 whenever signal Sx applied to the second input terminal of circuit C1-l is in a high-level state and when the signal ,Xcl applied to the other input terminal changes from a high level to a low level. H I i In a similar manner signal isvapplied. to the other input terminall of pulse-and circuit CEO-2; circuit Cx-Z being operative to produceV negative triggering signals on `leadsv30 and 40 when signal ris in a; highlevel-state and when signal X1 changes from a high level to a low level. v
While a particular form of pulse-and circuits Clm-l and C11-2 is shown in Fig. Sc, these circuits will not be described in further detail since they are described a'nd claimed .in"copending patent application Serial No. 327,133 for 'Diode, Pulse-Gating Circuits by Richard D. Forrest, filed December 20, 1952.
Essentially carry circuit C1x may be defined as providing the following operation:
(C13) 1X2=0Xc =sx.txcl+.v, where the signals PX1 and DLX-01 indicate negative-going pulse changes created when signal X1 changes from a high level to a low level and when signal X1 changes from a high level to a low level, respectively.
The first counting stage X1 is triggered successively by each 'motion signal Px. Thus, stage X1 is triggered successiyely on and ofi by successive motion pulses durpositioning of the carriage.
.. 19 ing the X carriage motion. Counting stage X9; then `is triggered on and off whenever a carryzsignal .is developed by circuit Clx. During counting-up Operations or .positive X carriage motion a binary carry signal is effective to trigger stage Xcz whenever signal Xci changes from high level to low level. During count-down Operations, or negative carriage motion, stage Xcz is triggered successively on and off for eachoccurrence or change .in signal X0, from a high level to a low level providing the desired count down carry. In a similar manner each 'of the other carry stages Cix actuates the corresponding counting stage whenever theV preceding counting stage changes from a high level to a low level during countingup Operations and from a low level to a high level during counting-down Operations.
The complete counting functions of the binary updown counter of Fig. 8a may then be sumrnarized as follows:
RELATIVE ADDRESS SYSTEM Reference is now made to Figs. 9 and 9a which illustrate in schematic form a punch address and comparison circuit 130X in accordance with a relative address method of control. Fig. 9 illustrates the entire circuit whereas Fig. 9a illustrates in greater detail a combined shifting register and counter circuit suitable for use in the circuit of Fig. 9. Before considering the circuits in detail it will 'be helpful to discu-ss the general characteristics of the relative address method of control.
According to the relative address method each instruction takes account only of the relative address, which may be defined as the difference between the previously vdesired carriage position and the presently desire carriage position. It is therefore convenient to utilize the instruction to preset a counter circuit whereby the number of counts remaining between the preset count and a predetermined comparison count is equal to the relative address. The counter must be mechanized to count in one particular direction, which may be either up or down. If the counter is mechanized to count down, then it must be preset at a count corresponding to the compariso-n count plus the relative address; for example, where the comparison count is and the relative address is 102, the counter must be preset to a count of 102. If on the other hand the counter is mechanided to count up, then the preset count must be less than' the comparison count by the amountof the relative address; for example, if a counter having a maximum capacity of 127 counts is utilized, with 127 as the comparison count, and if 102 mils ofl carriage travel is desired, then thecounter must be preset to a count of 25.
In the circuits specifically shown and described herein the counter is mechanized to count up. A maximum count of 3999 is pro-vided in order to permit a total carriage travel of 3999 mils. The zero o-r 4000th count is utilized as the comparison count, hence each address is entered as the 4000'8 complement of the associated relative address.
According to the system of Fig. l `the relative address method of control requires additional circuitry in order to provide reduced-speed operation, and in order to p0- sition 'the carriage in a VVrnan'ner which will` compensate for any error which may have occurred in the previous Thus, in its general form thel circuit of Fig. 9 includes. a counter and shifting register 136X; a motion-starting comparison circuit 137X; a reduced-speed comparison circuit 138x; an error-compen'sating and stopping' comparison circuit 140x; and
v20 motion control fiip-flops SX and MX. Counter `136x and flip-flop SX .together comprise a static' storage regis- ,ter into which a complete X address may be shifted.
Shifting register and counter 136X receives an X address during phase .III (the shifting being synchronizied by .means oftclock pulses Cp from program unit and during carriage motion counts in a predetermined cycle in response .to digital motion pulses Px received from motion detector 160X. Since the X address supplied to circuit 136X specifies the next desired carriage location with respect to the previously desired location, there is one numerical value of the address which corresponds to the situation' where no carriage `motion is desired. For any other value of the address, comparison circuit 137X produces a signal for setting flip-flop MX to 1 in order to initiate carriage motion. The reduced speed signal Mxr is produced by co-mparison circuit 138X when the carriage reaches a predetermined distance from the stopping point. At the desired stopping point, computed by taking into account any error in the previous carriage position, circuit 140X produces the stop signal Cxs for setting flip-flop MX to O in order to stop the X carriage.
A variety of'codes are of course possible for specifying the addresses and for performing the various functions of the circuit of Fig. 9. The specific code which has been selected for illustration, however, is the binary-coded decimal system wherein a separate series of four bits is utilized to represent each decirnal digit. More specifically, the bits within each series are assign'ed decimal weights of 1, 2, 4, and 8, respectively, in accordance with the straight binary code. Circuit 136x is assumed to have a total count capacity of 3999 and therefore includes 14 stages designated as X11, X21, X41, X231, X110, X210, X21000. Circuit 136X when Operating as a counter during carriage motion is responsive to motion signals Px-to count up; the stopping comparison is made by circuit 140x in order to stop the carriage o-n the zero or 40`00th count; therefore, each address is specified as the 4000'8 complement of the relative address, as previously defined. For example, if the previously desired position of the X carriage corresponded to an absolute reference point of 250 mils and the carriage is to be moved to an absolute reference point corresponding to 475 mils, the X address appears in' the instruction as follows:
X address=4000- (475 250) Sac 3 7 7 5 1 0011 0111 011.1 0101 In accordance with this method of representing a defsired address, comparison circuit 137X produces an output signal Nza for setting the carriage in motion whenever a non-zero address is shifted into the counter. comparison circuit 140X is mechanized to produce stopping signal Cxs when. counter 136X reaches the full or 0 state, corresponding'to a count of 4000, in the absence of an error in the previous carriage position. The reduced speed co-mparison circuit 138X is mechanized to produce and maintain reduced-speed signal Mxr throughout a specified amount of carriage travel, for example, the last ,100 mils.
For reasons which .will be explained herein'after, comparison signal Nza is produced by circuit 137X one time interval before the instruction has been completely shifted in. At this time the first (most significant) bit of the X address has been shifted into flip-flop Xlwog, hence the last (least significant) bit is stored at that time interval in the last fiip-fiop SY of circuit 134W. Accordingly, the comparison function for producing signal Nza, and
which defines the structure of circuit 13'7X, may be eX- Also,
in response to a signal produced by its l-input circuit IMX defined as follows:
Thus, in order for flip-fiop MX to be set to 1 the marker bit must not have reached flip-flop RC (see Fig. 2); signal Sx must be 1 indicating that the marker bit is stored in flip-fiop SX; signal Nza must be 1 indicating a nonzero address; and the clock pulse Cp must be present. The reason for this mechanization isthat even if the address were a signal Nza would be produced in response to the shifting of the marker bit through circuit 136X. Hence, the mechanization of circuit lMX'provides for triggering flp-flop MX to V1 during a specific time interval when the location of the marker bit is specified, namely, When the marker bit is in flip-fiop SX during the time interval preceding its arrival in fiip-flop RC. It would also be possible to trigger fiip-fiop MX one time interval later; however, as previously pointed out in connection with Fig. 2 the clock pulses Cp are unavailable after the arrival of the marker bit in fiip-fiop RC, hence it would be necessary in such case to reset the flip-fiop by means of its Ja input circuit rather than the J or conventional l-input circuit.
Comparison circuit 138X has a fixed mechanization for providing reduced-speed operation throughout the last 100 mils of carriage travel. Thus, the function for signal MXR, and which defines the structure of circuit 138X, may be expressed as follows:
(138x) MXR=X21000'Xlmoo'Xaloo'Xlloo'Rc the above mechanizaiton providing a comparison to indate whenever the count stored in counter 136X is 3900 or greater, namely, any count from 3900 to 3999, inclusive.
The structure and function of error-compensating and stopping-comparison circuit 140X will now be explained. Circuit 140X includes an enabling network 141X; an error counter 142 X; a sign storage unit 143X; and an output comparison circuit 144X. The purpose of the enabling network 141X is to permit the error counter to operate in response to motion pulses Px during the terminal portion of carriage travel so as to recognize any over-travel. The error counter 142X itself is reversible in response to sign signals Sx and 5x to count either up or down according to the direction of carriage motion. Sign storage unit 143X is provided for storing the sign digit of the previous instruction, since the method of compensating for any previous over-travel obviously depends upon whether the present direction of carriage travel is the same as, or different from, the previous direction. Finally, output comparison circuit 144X produces an output signal Cxs for stopping the carriage motion When the desired position in accordance with the present instruction has been reached.
The design'of circuit 140X is based upon the assumption that a maximum of 3 mils of over-travel is possible in stopping the carriage at any particular location, hence the error counter includes two binary stages for representing any decimal count from 0 to 3, inclusive. The counter is mechanized to count up when carriage motion is positive (Sx=l) and to count down when carriage motion is negative (=1). In the normal operation of the counter, when there has been no carriage over-travel in performing the preceding instruction, the error counter is initially in its 0 state and is enabled by circuit 141X during count 3996 of counter 136X. Thus, in response to the next four motion pulses Px, counter 136X counts through the remainder of its cycle back to 0; the error counter counts from 0 to 1, 2, 3, and back to 0; and upon the return of the error counter to its zero state, comparison circuit 144X produces signal Cxs for stopping the carriage.
, Before describing the error counter in detail it will be expedient to briefiy describe the enabling network 141X.
Enabling network 141'X includes a flip-flop X3996 and a comparison circuit C3995l for setting the associated fiip-fiop to l. The comparison circuit develops an output signal in response to the 3995th count state existing in counter 136X, and the next motion pulse Px, which sets counter 136X to count 3996, also triggers the fiip-flop X3996 to 1. The expression for the comparison signal is as follows:
After completion of the punch flip-flop X3996 must be reset by signal Do, hence The output signal of fiip-flop X3996 is applied to both stages of the error counter 142X for enabling it to operate after the appearance of the 3996th count state in counter 136x until reset signal Do is produced upon completion of the punch.
Error counter 142X includes two flip-fiop C1x and C2x representing the less significant and the more significant binary digits, respectively. Flip-flop C1x is triggered continuously during the enabling period in response to each motion pulse Px. The mechanization of the input circuits of fiip-flop'C2x is such as to provide counting up when Sx is 1, and counting down when Sx is l. Accordingly the rnechanization functions are as follows:
1C1=0C1x=X399spx (142X) 1C2=0C2m=(Sx-C1`.+Sx' C13) 'X3996 'Px The complete counting cycle is given in Table VII.
Table VII Decimal Count C2, C1, Count Up Count Down It is apparent that whereas the error counter is normally operative to count through its entire cycle before the stopping signal Cxs is produced, in the event of over-travel of the carriage in performing the preceding instruction this normal counting cycle must be either diminished or augmented. More specifically, where the carriage direction is the same in both instan'ces the normal counting cycle must be diminished by the amount of the over-travel, but where the carriage direction is different for the two instructions the normal counting cycle must be augmented by the amount of the over-travel.
Sign storage unit 143X includes a flip-fiop PX and three logical gating circuits for controlling the l and 0 input circuits thereof. The sign digit of the previous in- 'struction must be available in flip-flop Spx for determining the proper error compensation to be made in carrying out the present instruction; therefore, the sign digit of the present instruction must, at some time while it is still available, be shifted into fiip-flop SPX. The timing of this shifting operation is of critical importance.
It has previously been pointed out that during the enabling period and prior to the time when stop signal Cxs is produced the error counter 142X must count either a full cycle less previous over-travel, or a full cycle plus previous over-travel. The manner in which the counting cycle takes place, and the shifting of the sign digit into flip-fiop SDK, will be explained in the following paragraphs in conjunction with subsequent Table VIII.
Where the previous and present directions of carriage motion are the same, as indicated by signals Sx and SPx being equal, only a full cycle minus the previous overtravel is required. When the error counter 142X reaches